Metallization interconnects are critical to the proper electronic function of semiconductor devices. Several advances in integrated circuit manufacturing processing have been aimed at improving signal transport speed by reducing metal interconnect resistivities and improving resistance to electromigration effects. Copper has increasingly become a metal of choice in, for example, upper levels of metallization in a multi-level semiconductor device due to its low resistivity. Tungsten (W), however, has been used in the lower metallization layers, for example the PMD layer to form plugs or vias to contact underlying conductive areas including CMOS source and drain regions since it provides an effective diffusion barrier to metal diffusion from overlying copper metallization layers. Tungsten further has had acceptable resistance to electromigration in characteristic device dimensions of greater than about 0.25 microns and can effectively fill high aspect ratio vias by chemical vapor deposition (CVD) processes.
As device characteristic dimensions shrink, however, the prior art practice of forming tungsten plugs in lower metallization layers creates several problems. For example, the cost and complexity of processing increases, requiring increasingly complex processing including tungsten deposition, tungsten dry etchback, and/or CMP planarization processes to avoid respectively, for example, voids in tungsten plugs, tungsten particle contamination, and the formation of tungsten metal stringers. In addition, the electrical performance properties of tungsten, including electrical resistance are less than adequate for characteristic device dimensions less than about 0.25 microns. Moreover, the high temperature deposition processes currently required for tungsten as well as overlying conventional copper metallization leads to undesirable defects in previously deposited metallization layers.
Therefore, there is a need in the semiconductor processing art to develop an improved integrated circuit wiring structure and method for forming the same to achieve improved electrical performance as well as decreased processing complexity.
It is therefore an object of the invention to provide an improved integrated circuit wiring structure and method for forming the same to achieve improved electrical performance as well as decreased processing complexity, while overcoming other shortcomings of the prior art.